EP610PC25 vs EP610LC-25 Comparison
Detailed side-by-side comparison of EP610PC25 by Altera and EP610LC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC25 | EP610LC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Logic Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | — |
| Programming Voltage (VPP) | 12 V | — |
| ICC (typical) | 200 mA | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | PDIP-24 | PLCC-28 |
| Mounting Type | Through-Hole | Surface Mount |
| Programmability | One-Time-Programmable (OTP), UV-erasable variant exists | UV-erasable (windowed package) |
| Pin Count | 24 | — |
| Technology | 5 V CMOS | CMOS |
| RoHS Status | unknown | [DATA_NEEDED] |
| Lifecycle | Obsolete (last shipped ~2000s) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EPLD |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Toggle Frequency | — | 100 MHz |
| Supply Voltage | — | 5 V ±5% |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |