EP610PC25 vs EP610LC-25 比較
詳細並排比較 EP610PC25 由 Altera 與 EP610LC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC25 | EP610LC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Logic Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | — |
| Programming Voltage (VPP) | 12 V | — |
| ICC (typical) | 200 mA | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 封裝 | PDIP-24 | PLCC-28 |
| 安裝類型 | Through-Hole | Surface Mount |
| Programmability | One-Time-Programmable (OTP), UV-erasable variant exists | UV-erasable (windowed package) |
| 腳位數 | 24 | — |
| Technology | 5 V CMOS | CMOS |
| RoHS 狀態 | unknown | [DATA_NEEDED] |
| Lifecycle | Obsolete (last shipped ~2000s) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EPLD |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Toggle Frequency | — | 100 MHz |
| 供應電壓 | — | 5 V ±5% |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |