EP910DC-15 vs EP910DC-35 Comparison
Detailed side-by-side comparison of EP910DC-15 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-15 | EP910DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD EP910 |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Operating Temperature | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Technology | CMOS EPROM, UV-erasable | CMOS, UV-erasable EPROM cell |
| Package | 24-pin ceramic DIP (DC) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Mounting Type | Through-Hole | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: not explicitly stated in verified data] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Clock Frequency | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |