EP910DC-15 vs EP910DC-35 Vergleich

Detaillierter Direktvergleich von EP910DC-15 von Altera und EP910DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DC-15 EP910DC-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,75 $10,95
Family Altera Classic EPLD Classic EPLD EP910
Device Density 900 usable gates —
Macrocells 24 24
Logic Elements [DATA_NEEDED: exact LE count] —
Dedicated Inputs 12 12
Bidirectional I/O Pins 12 —
Flip-Flops 10 —
Product Terms per Macrocells 24 —
Maximum Propagation Delay (tPD) 15 ns —
Speed Grade 15 —
Supply Voltage (VCC) 5 V (typical) —
Betriebstemperatur 0C to +70C (commercial) 0 °C to +70 °C (commercial)
Technology CMOS EPROM, UV-erasable CMOS, UV-erasable EPROM cell
Gehäuse 24-pin ceramic DIP (DC) 40-pin CDIP (Ceramic DIP) with quartz window
Montageart Through-Hole —
MSL-Level [DATA_NEEDED: MSL level] —
RoHS-Status [DATA_NEEDED: not explicitly stated in verified data] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maximale Taktfrequenz — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Lifecycle — Obsolete / last-time-buy from authorized distributors

Datenblätter & Ressourcen

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