EP910DC-15 vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-15 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DC-15 EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD Classic EPLD EP910
Device Density 900 usable gates —
Macrocells 24 24
Logic Elements [DATA_NEEDED: exact LE count] —
Dedicated Inputs 12 12
Bidirectional I/O Pins 12 —
Flip-Flops 10 —
Product Terms per Macrocells 24 —
Maximum Propagation Delay (tPD) 15 ns —
Speed Grade 15 —
Supply Voltage (VCC) 5 V (typical) —
Temperature na Operasyon 0C to +70C (commercial) 0 °C to +70 °C (commercial)
Technology CMOS EPROM, UV-erasable CMOS, UV-erasable EPROM cell
Packhaging 24-pin ceramic DIP (DC) 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Through-Hole —
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: not explicitly stated in verified data] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Lifecycle — Obsolete / last-time-buy from authorized distributors

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