EP910DC-30 vs EP910IDI-15 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-30 | EP910IDI-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $29.00 |
| Family | Classic EPLD (EP910 series) | Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | β |
| Gate Count | 900 usable gates | β |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Clock Frequency (fCNT) | 33.3 MHz | β |
| Dedicated Inputs | 36 | β |
| Outputs (Macrocells) | 24 | β |
| External Clock Pins | 2 (CLK1, CLK2) | β |
| Supply Voltage | 5 V | β |
| Process Technology | CMOS | β |
| Programming Method | UV-Erasable / OTP | β |
| Package | DIP-40 (through-hole, 600 mil) | 40-pin CDIP (CerDIP) with quartz window |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial, "I" grade) |
| Mounting Type | Through-Hole | Through-hole (DIP) |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 450 gates |
| Maximum User I/O Pins | β | 36 |
| Pin-to-Pin Propagation Delay (tpd) | β | 15 ns |
| Maximum Counter Frequency | β | 66.6 MHz |
| Supply Voltage (Vcc) | β | 5 V |
| Technology | β | CMOS EPROM |
| Program/Erase Method | β | UV-erasable windowed CerDIP |
| Macrocells Configurable As | β | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | β | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | β | Altera Logic Programmer card |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Logic Family Compatibility | β | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |