EP910DC-30 vs EP910IDI-15 比較
詳細並排比較 EP910DC-30 由 Intel 與 EP910IDI-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DC-30 | EP910IDI-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | — |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | — |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| 供應電壓 | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | — |
| 封裝 | DIP-40 (through-hole, 600 mil) | 40-pin CDIP (CerDIP) with quartz window |
| 工作溫度 | 0C to +70C (commercial) | -40C to +85C (industrial, "I" grade) |
| 安裝類型 | Through-Hole | Through-hole (DIP) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 gates |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EPROM |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |