EP910DC-30 vs EP910IDI-15 Vergleich

Detaillierter Direktvergleich von EP910DC-30 von Intel und EP910IDI-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DC-30 EP910IDI-15
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $15,60 $29,00
Family Classic EPLD (EP910 series) Classic EPLD
Architecture PAL-type AND-OR sum-of-products, CMOS —
Gate Count 900 usable gates —
Macrocells 24 24
Propagation Delay (tPD) 30 ns (max) —
Clock Frequency (fCNT) 33.3 MHz —
Dedicated Inputs 36 —
Outputs (Macrocells) 24 —
External Clock Pins 2 (CLK1, CLK2) —
Versorgungsspannung 5 V —
Process Technology CMOS —
Programming Method UV-Erasable / OTP —
Gehäuse DIP-40 (through-hole, 600 mil) 40-pin CDIP (CerDIP) with quartz window
Betriebstemperatur 0C to +70C (commercial) -40C to +85C (industrial, "I" grade)
Montageart Through-Hole Through-hole (DIP)
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 450 gates
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Supply Voltage (Vcc) — 5 V
Technology — CMOS EPROM
Program/Erase Method — UV-erasable windowed CerDIP
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
RoHS-Status — [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

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