EP910DC-35 vs EP910DM-40 Comparison

Detailed side-by-side comparison of EP910DC-35 by Altera and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DC-35 EP910DM-40
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.95 $21.00
Device Type UV-Erasable CMOS PLD (PAL-type) β€”
Family Classic EPLD EP910 Altera Classic EP910
Architecture PAL-type sum-of-products AND-OR array PAL-type AND/OR with global programmable interconnect bus
Usable Gates 900 gates β€”
Macrocells 24 24
Product Terms 240 240
Dedicated Inputs 12 36
I/O Pins 24 β€”
Total Inputs 36 β€”
Propagation Delay (tpd) 35 ns β€”
Maximum Clock Frequency 37 MHz (typical, internal) β€”
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) [DATA_NEEDED: operating temperature range]
Package 40-pin CDIP (Ceramic DIP) with quartz window 40-pin Ceramic DIP (Cerdip) with UV window
Lead Pitch 2.540 mm β€”
Termination Style Through-Hole β€”
Programming Method JEDEC fuse map via device programmer; UV erase β€”
Technology CMOS, UV-erasable EPROM cell β€”
RoHS Status Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: RoHS compliance status]
Lifecycle Obsolete / last-time-buy from authorized distributors β€”
Product Type β€” UV Erasable Programmable Logic Device (EPLD)
Dedicated Outputs β€” 24
Bidirectional I/O Lines β€” 24
Propagation Delay (tPD) β€” 40 ns
External Clocks β€” 2
Process Technology β€” CMOS
Mounting Type β€” Through-Hole (DIP)
Supply Voltage β€” 5 V
Programming Interface β€” JEDEC-standard fuse-map / UV erasure

Datasheets & Resources

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