EP910DC-35 vs EP910DM-40 तुलना
विस्तृत दोनों ओर की तुलना EP910DC-35 द्वारा Altera और EP910DM-40 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910DC-35 | EP910DM-40 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | Altera Classic EP910 |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type AND/OR with global programmable interconnect bus |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 |
| Dedicated Inputs | 12 | 36 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| अधिकतम क्लॉक फ़्रीक्वेंसी | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| ऑपरेटिंग तापमान | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| पैकेज | 40-pin CDIP (Ceramic DIP) with quartz window | 40-pin Ceramic DIP (Cerdip) with UV window |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | — |
| RoHS स्थिति | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| माउंटिंग प्रकार | — | Through-Hole (DIP) |
| सप्लाई वोल्टेज | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |