EP910DC-35 vs EP910IDC-15 Comparison

Detailed side-by-side comparison of EP910DC-35 by Altera and EP910IDC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DC-35 EP910IDC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.95 $9.95
Device Type UV-Erasable CMOS PLD (PAL-type) β€”
Family Classic EPLD EP910 Classic EPLD
Architecture PAL-type sum-of-products AND-OR array β€”
Usable Gates 900 gates β€”
Macrocells 24 24
Product Terms 240 β€”
Dedicated Inputs 12 10
I/O Pins 24 24
Total Inputs 36 β€”
Propagation Delay (tpd) 35 ns β€”
Maximum Clock Frequency 37 MHz (typical, internal) β€”
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) β€”
Package 40-pin CDIP (Ceramic DIP) with quartz window 40-pin CDIP (Ceramic DIP, through-hole)
Lead Pitch 2.540 mm β€”
Termination Style Through-Hole β€”
Programming Method JEDEC fuse map via device programmer; UV erase β€”
Technology CMOS, UV-erasable EPROM cell β€”
RoHS Status Non-compliant (ceramic DIP with Pb-bearing lead finish) non_compliant (ceramic DIP contains lead)
Lifecycle Obsolete / last-time-buy from authorized distributors β€”
Manufacturer β€” Altera (now Intel PSG)
Equivalent Gates β€” 450
Flip-Flops β€” 48
Pin-to-Pin Delay (tPD) β€” 15 ns
Maximum Frequency (fCNT) β€” 66.6 MHz
Supply Voltage (VCC) β€” 5 V
Terminal Count β€” 40
Terminal Form β€” Through-Hole
Temperature Grade β€” Commercial (0C to +70C)
Programmable Security Bit β€” Yes
On-board Test Circuitry β€” Yes
Logic Type β€” UV Erasable EPROM-based
Programming Technology β€” EPROM (UV-erasable)

Datasheets & Resources

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