EP910DC-35 vs EP910IDC-15 Vergleich

Detaillierter Direktvergleich von EP910DC-35 von Altera und EP910IDC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DC-35 EP910IDC-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,95 $9,95
Device Type UV-Erasable CMOS PLD (PAL-type) —
Family Classic EPLD EP910 Classic EPLD
Architecture PAL-type sum-of-products AND-OR array —
Usable Gates 900 gates —
Macrocells 24 24
Product Terms 240 —
Dedicated Inputs 12 10
I/O Pins 24 24
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
Maximale Taktfrequenz 37 MHz (typical, internal) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) —
Betriebstemperatur 0 °C to +70 °C (commercial) —
Gehäuse 40-pin CDIP (Ceramic DIP) with quartz window 40-pin CDIP (Ceramic DIP, through-hole)
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase —
Technology CMOS, UV-erasable EPROM cell —
RoHS-Status Non-compliant (ceramic DIP with Pb-bearing lead finish) non_compliant (ceramic DIP contains lead)
Lifecycle Obsolete / last-time-buy from authorized distributors —
Manufacturer — Altera (now Intel PSG)
Equivalent Gates — 450
Flip-Flops — 48
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fCNT) — 66.6 MHz
Supply Voltage (VCC) — 5 V
Terminal Count — 40
Terminal Form — Through-Hole
Temperature Grade — Commercial (0C to +70C)
Programmable Security Bit — Yes
On-board Test Circuitry — Yes
Logic Type — UV Erasable EPROM-based
Programming Technology — EPROM (UV-erasable)

Datenblätter & Ressourcen

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