EP910DC-40 vs EP910DC-15 Comparison
Detailed side-by-side comparison of EP910DC-40 by Altera and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-40 | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.95 | $10.75 |
| Device Family | Classic EPLD (EP910 series) | β |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | 12 |
| Total Inputs to Logic Array | 36 | β |
| Product Terms | 240 maximum | β |
| Maximum Propagation Delay (tPD) | 40 ns | 15 ns |
| Maximum Operating Frequency (fMAX) | 25 MHz | β |
| Global Clocks | 2 | β |
| Supply Voltage | 5 V (typical for Classic EPLD family) | β |
| Operating Temperature (Commercial) | 0 Β°C to 70 Β°C | β |
| Package | DIP-40 (ceramic, through-hole) | 24-pin ceramic DIP (DC) |
| Mounting Type | Through-Hole | Through-Hole |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | β |
| Family | β | Altera Classic EPLD |
| Device Density | β | 900 usable gates |
| Logic Elements | β | [DATA_NEEDED: exact LE count] |
| Flip-Flops | β | 10 |
| Product Terms per Macrocells | β | 24 |
| Speed Grade | β | 15 |
| Supply Voltage (VCC) | β | 5 V (typical) |
| Operating Temperature | β | 0C to +70C (commercial) |
| Technology | β | CMOS EPROM, UV-erasable |
| MSL Level | β | [DATA_NEEDED: MSL level] |