EP910DC-40 vs EP910DC-15 Vergleich
Detaillierter Direktvergleich von EP910DC-40 von Altera und EP910DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910DC-40 | EP910DC-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $13,95 | $10,75 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | 12 |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | 15 ns |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Versorgungsspannung | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Gehäuse | DIP-40 (ceramic, through-hole) | 24-pin ceramic DIP (DC) |
| Montageart | Through-Hole | Through-Hole |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Family | — | Altera Classic EPLD |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Betriebstemperatur | — | 0C to +70C (commercial) |
| Technology | — | CMOS EPROM, UV-erasable |
| MSL-Level | — | [DATA_NEEDED: MSL level] |