EP910DC-40 vs EP910DC-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DC-40 disebabkan oleh Altera dan EP910DC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910DC-40 | EP910DC-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | 12 |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | 15 ns |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Tegangan Pemberi Arus | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Kemasan | DIP-40 (ceramic, through-hole) | 24-pin ceramic DIP (DC) |
| Jenis Pemasangan | Through-Hole | Through-Hole |
| Status RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Family | — | Altera Classic EPLD |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Suhu Operasi | — | 0C to +70C (commercial) |
| Technology | — | CMOS EPROM, UV-erasable |
| Aras MSL | — | [DATA_NEEDED: MSL level] |