EP910DC-40 vs EP910DC-15 Comparaison
Comparaison détaillée côte à côte de EP910DC-40 par Altera et EP910DC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910DC-40 | EP910DC-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,95 | $10,75 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | 12 |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | 15 ns |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Tension d'alimentation | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Boîtier | DIP-40 (ceramic, through-hole) | 24-pin ceramic DIP (DC) |
| Type de montage | Through-Hole | Through-Hole |
| Statut RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Family | — | Altera Classic EPLD |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Température de fonctionnement | — | 0C to +70C (commercial) |
| Technology | — | CMOS EPROM, UV-erasable |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |