EP910DC-40 vs EP910DM-40 Comparison
Detailed side-by-side comparison of EP910DC-40 by Altera and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-40 | EP910DM-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Supply Voltage | 5 V (typical for Classic EPLD family) | 5 V |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Package | DIP-40 (ceramic, through-hole) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EP910 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |