EP910DC-40 vs EP910DM-40 比較
詳細並排比較 EP910DC-40 由 Altera 與 EP910DM-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DC-40 | EP910DM-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| 供應電壓 | 5 V (typical for Classic EPLD family) | 5 V |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| 封裝 | DIP-40 (ceramic, through-hole) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| RoHS 狀態 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EP910 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |