EP910DC-40 vs EP910DM-40 比較
詳細な並列比較: EP910DC-40 メーカー: Altera および EP910DM-40 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DC-40 | EP910DM-40 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $13.95 | $21.00 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND/OR with global programmable interconnect bus |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| 電源電圧 | 5 V (typical for Classic EPLD family) | 5 V |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| パッケージ | DIP-40 (ceramic, through-hole) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 実装タイプ | Through-Hole | Through-Hole (DIP) |
| RoHS ステータス | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EP910 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| 動作温度 | — | [DATA_NEEDED: operating temperature range] |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |