EP910DC-40 vs EP910JM-40 Comparison
Detailed side-by-side comparison of EP910DC-40 by Altera and EP910JM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-40 | EP910JM-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.95 | $9.95 |
| Device Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | β |
| Total Inputs to Logic Array | 36 | β |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | β |
| Maximum Operating Frequency (fMAX) | 25 MHz | β |
| Global Clocks | 2 | β |
| Supply Voltage | 5 V (typical for Classic EPLD family) | β |
| Operating Temperature (Commercial) | 0 Β°C to 70 Β°C | β |
| Package | DIP-40 (ceramic, through-hole) | JLCC-28 (windowed ceramic, J-lead) |
| Mounting Type | Through-Hole | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | UV erase + EPROM programmer |
| Series | β | EP910 |
| Logic Type | β | EPLD (UV-Erasable PAL-type) |
| I/O Lines | β | 24 |
| Total Inputs (max) | β | 36 |
| Total Outputs (max) | β | 24 |
| External Clock Inputs | β | 2 |
| Propagation Delay (tPD) | β | 40 ns |
| Process Technology | β | CMOS |
| Operating Temperature | β | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] |