EP910DC-40 vs EP910JM-40 Perbandingan
Perbandingan bersamaan detil EP910DC-40 dari Altera dan EP910JM-40 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910DC-40 | EP910JM-40 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Tegangan Pemuat | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Paket | DIP-40 (ceramic, through-hole) | JLCC-28 (windowed ceramic, J-lead) |
| Tipe Mounting | Through-Hole | Surface Mount |
| Status RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | UV erase + EPROM programmer |
| Series | — | EP910 |
| Logic Type | — | EPLD (UV-Erasable PAL-type) |
| I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| External Clock Inputs | — | 2 |
| Propagation Delay (tPD) | — | 40 ns |
| Process Technology | — | CMOS |
| Suhu Kerja | — | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] |