EP910ILC-15N vs EP910ILC-12 Comparison
Detailed side-by-side comparison of EP910ILC-15N by Altera and EP910ILC-12 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Specification Comparison
| Parameter | EP910ILC-15N | EP910ILC-12 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $12.40 |
| Family | Classic | Altera EP910 Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Gates | 450 | β |
| Macro Cells | 24 | β |
| Maximum Propagation Delay (tPD) | 15 ns | β |
| Maximum Operating Frequency | 66.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| User I/O Pins | 36 | β |
| Dedicated Input Pins | 16 | β |
| Package | PLCC-44 (J-lead, surface mount) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) | -40 Β°C to +85 Β°C (industrial grade, 'I' suffix) |
| Process Technology | CMOS EPROM (one-time programmable) | β |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Programming | EPROM / JTAG (Classic EP-series) | β |
| Number of Macrocells | β | 24 |
| Usable Gates | β | 450 (typical) |
| Propagation Delay (tPD) | β | 12 ns (max) |
| Nominal Supply | β | 5 V |
| Memory Technology | β | UV-erasable CMOS EPROM |
| Configuration Storage | β | Non-volatile EPROM (instant-on) |
| Programming Method | β | Altera programming algorithm (serial/parallel master-slave) |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Number of Pins | β | 28 |
| Feedback Paths | β | 16 dedicated |