EP910ILC-15N vs EP910ILC-12 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15N sa pamamagitan ng Altera at EP910ILC-12 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910ILC-15N EP910ILC-12
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Classic Altera EP910 Classic EPLD
Product Type CPLD (Complex Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Logic Gates 450 —
Macro Cells 24 —
Maximum Propagation Delay (tPD) 15 ns —
Maximum Operating Frequency 66.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V
User I/O Pins 36 —
Dedicated Input Pins 16 —
Packhaging PLCC-44 (J-lead, surface mount) 28-PLCC (J-Lead, 11.5 x 11.5 mm)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0 C to +70 C (commercial) -40 °C to +85 °C (industrial grade, 'I' suffix)
Process Technology CMOS EPROM (one-time programmable) —
JTAG Support IEEE 1149.1 boundary-scan —
Tindminan RoHS Compliant [DATA_NEEDED: RoHS status]
Programming EPROM / JTAG (Classic EP-series) —
Number of Macrocells — 24
Usable Gates — 450 (typical)
Propagation Delay (tPD) — 12 ns (max)
Nominal Supply — 5 V
Memory Technology — UV-erasable CMOS EPROM
Configuration Storage — Non-volatile EPROM (instant-on)
Programming Method — Altera programming algorithm (serial/parallel master-slave)
Level ng MSL — [DATA_NEEDED: MSL level]
Bilang ng Pins — 28
Feedback Paths — 16 dedicated

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