EP910ILC-15N vs EP910ILC-12 比較
詳細並排比較 EP910ILC-15N 由 Altera 與 EP910ILC-12 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
規格比較
| 參數 | EP910ILC-15N | EP910ILC-12 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic | Altera EP910 Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| User I/O Pins | 36 | — |
| Dedicated Input Pins | 16 | — |
| 封裝 | PLCC-44 (J-lead, surface mount) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 C to +70 C (commercial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 (typical) |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| 腳位數 | — | 28 |
| Feedback Paths | — | 16 dedicated |