EP910ILC-50 vs EP910JM-40 Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910JM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-50 | EP910JM-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.85 | $9.95 |
| Family | Altera Classic EPLD | β |
| Macrocells | 24 | 24 |
| Usable Gates | 900 (typical) | β |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | β |
| Pin-to-Pin Delay (tpd) | 50 ns | β |
| Supply Voltage (VCC) | 5 V (typical) | β |
| User I/O Pins | 24 | β |
| Dedicated Input Pins | 12 | β |
| Package | PLCC-44 (J-lead) | JLCC-28 (windowed ceramic, J-lead) |
| Mounting Type | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] |
| Programming Cycles | 100 (minimum) | β |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] |
| Device Family | β | Altera Classic EPLD |
| Series | β | EP910 |
| Logic Type | β | EPLD (UV-Erasable PAL-type) |
| Dedicated Inputs | β | 12 |
| I/O Lines | β | 24 |
| Total Inputs (max) | β | 36 |
| Total Outputs (max) | β | 24 |
| Product Terms | β | 240 |
| External Clock Inputs | β | 2 |
| Propagation Delay (tPD) | β | 40 ns |
| Process Technology | β | CMOS |
| Programming Method | β | UV erase + EPROM programmer |