EP910ILC-50 vs EP910JM-40 Vergleich
Detaillierter Direktvergleich von EP910ILC-50 von Intel und EP910JM-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910ILC-50 | EP910JM-40 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,85 | $9,95 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| Gehäuse | PLCC-44 (J-lead) | JLCC-28 (windowed ceramic, J-lead) |
| Montageart | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] |
| Device Family | — | Altera Classic EPLD |
| Series | — | EP910 |
| Logic Type | — | EPLD (UV-Erasable PAL-type) |
| Dedicated Inputs | — | 12 |
| I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Product Terms | — | 240 |
| External Clock Inputs | — | 2 |
| Propagation Delay (tPD) | — | 40 ns |
| Process Technology | — | CMOS |
| Programming Method | — | UV erase + EPROM programmer |