EP910ILC-50 vs EP910JM-40 Comparação
Comparação detalhada lado a lado de EP910ILC-50 por Intel e EP910JM-40 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP910ILC-50 | EP910JM-40 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $10,85 | $9,95 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| Encapsulamento | PLCC-44 (J-lead) | JLCC-28 (windowed ceramic, J-lead) |
| Tipo de montagem | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | — |
| Temperatura de operação | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] |
| Device Family | — | Altera Classic EPLD |
| Series | — | EP910 |
| Logic Type | — | EPLD (UV-Erasable PAL-type) |
| Dedicated Inputs | — | 12 |
| I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Product Terms | — | 240 |
| External Clock Inputs | — | 2 |
| Propagation Delay (tPD) | — | 40 ns |
| Process Technology | — | CMOS |
| Programming Method | — | UV erase + EPROM programmer |