EP910JC-30 vs EP910LI-35 Comparison
Detailed side-by-side comparison of EP910JC-30 by Intel and EP910LI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-30 | EP910LI-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $25.80 |
| Family | Classic EPLD (MAX-style) | Altera Classic EPLD |
| Propagation Delay (tpd) | 30 ns | β |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| Product Terms | 240 | β |
| Outputs | 10 dedicated | β |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EPROM, UV-erasable | β |
| Package | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | 44-pin PLCC (J-lead) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40 Β°C to +85 Β°C (Industrial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | β |
| Mounting Type | Surface Mount (socket-mountable) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | β |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | β |
| Device Series | β | EP910 |
| Usable Gates | β | 900 |
| Maximum User I/O Pins | β | 38 |
| Propagation Delay (t_PD) | β | 35 ns |
| Maximum Counter Frequency (f_CNT) | β | 76.9 MHz |
| Supply Voltage | β | 5 V (4.75 V to 5.25 V) |
| Process Technology | β | CMOS EPROM |
| Programming Technology | β | EPROM (UV-erasable) |
| Erase/Program Cycles | β | β₯100 |
| Lead Pitch | β | 1.27 mm |