EP910JC-30 vs EP910LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910JC-30 sa pamamagitan ng Intel at EP910LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910JC-30 | EP910LI-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD (MAX-style) | Altera Classic EPLD |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Packhaging | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | 44-pin PLCC (J-lead) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (Industrial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| Uri ng Pagpapasok | Surface Mount (socket-mountable) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Volte ng Pagbibigay | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |