EP910JC-30 vs EP910LI-35 比較
詳細な並列比較: EP910JC-30 メーカー: Intel および EP910LI-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910JC-30 | EP910LI-35 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $25.80 |
| Family | Classic EPLD (MAX-style) | Altera Classic EPLD |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | — |
| パッケージ | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | 44-pin PLCC (J-lead) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (Industrial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| 実装タイプ | Surface Mount (socket-mountable) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| 電源電圧 | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |