EP910JC-30 vs EP910LI-35 Vergleich
Detaillierter Direktvergleich von EP910JC-30 von Intel und EP910LI-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910JC-30 | EP910LI-35 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $25,80 |
| Family | Classic EPLD (MAX-style) | Altera Classic EPLD |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Gehäuse | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | 44-pin PLCC (J-lead) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (Industrial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| Montageart | Surface Mount (socket-mountable) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Versorgungsspannung | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |