EP910JC-35 vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910JC-35 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910JC-35 EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $10.95
Logic Family Classic EPLD (CMOS EPROM) β€”
Macrocells 24 24
Inputs 36 β€”
I/O Pins 24 24
Propagation Delay (max) 38 ns (tPD) β€”
Maximum Clock Frequency 28.6 MHz 37 MHz (typical, internal)
Supply Voltage (VCC) 4.75 V to 5.25 V β€”
Operating Temperature 0C to 70C (Commercial) 0 Β°C to +70 Β°C (commercial)
Package Type 44-pin PLCC (Plastic J-Lead Chip Carrier) β€”
Mounting Type Surface Mount (PLCC socket recommended) β€”
Terminal Form J BEND β€”
Package Code QCCJ β€”
Package Shape SQUARE β€”
Technology CMOS EPROM, UV-erasable / OTP CMOS, UV-erasable EPROM cell
RoHS Status [DATA_NEEDED: rohs status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Temperature Grading COMMERCIAL β€”
Equivalent Gates Approx. 900 usable gates β€”
Device Type β€” UV-Erasable CMOS PLD (PAL-type)
Family β€” Classic EPLD EP910
Architecture β€” PAL-type sum-of-products AND-OR array
Usable Gates β€” 900 gates
Product Terms β€” 240
Dedicated Inputs β€” 12
Total Inputs β€” 36
Propagation Delay (tpd) β€” 35 ns
Supply Voltage (Vcc) β€” 4.75 V to 5.25 V (5 V nominal)
Package β€” 40-pin CDIP (Ceramic DIP) with quartz window
Lead Pitch β€” 2.540 mm
Termination Style β€” Through-Hole
Programming Method β€” JEDEC fuse map via device programmer; UV erase
Lifecycle β€” Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

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