EP910JC-35 vs EP910DC-35 Vergleich

Detaillierter Direktvergleich von EP910JC-35 von Altera und EP910DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910JC-35 EP910DC-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $10,95
Logic Family Classic EPLD (CMOS EPROM) —
Macrocells 24 24
Inputs 36 —
I/O Pins 24 24
Propagation Delay (max) 38 ns (tPD) —
Maximale Taktfrequenz 28.6 MHz 37 MHz (typical, internal)
Supply Voltage (VCC) 4.75 V to 5.25 V —
Betriebstemperatur 0C to 70C (Commercial) 0 °C to +70 °C (commercial)
Package Type 44-pin PLCC (Plastic J-Lead Chip Carrier) —
Montageart Surface Mount (PLCC socket recommended) —
Terminal Form J BEND —
Package Code QCCJ —
Package Shape SQUARE —
Technology CMOS EPROM, UV-erasable / OTP CMOS, UV-erasable EPROM cell
RoHS-Status [DATA_NEEDED: rohs status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Temperature Grading COMMERCIAL —
Equivalent Gates Approx. 900 usable gates —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Family — Classic EPLD EP910
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Product Terms — 240
Dedicated Inputs — 12
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Gehäuse — 40-pin CDIP (Ceramic DIP) with quartz window
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Lifecycle — Obsolete / last-time-buy from authorized distributors

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