EP910JC-35 vs EP910DC-35 对比
详细并排对比 EP910JC-35 出自 Altera 和 EP910DC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910JC-35 | EP910DC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $10.95 |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| I/O Pins | 24 | 24 |
| Propagation Delay (max) | 38 ns (tPD) | — |
| 最大时钟频率 | 28.6 MHz | 37 MHz (typical, internal) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作温度 | 0C to 70C (Commercial) | 0 °C to +70 °C (commercial) |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| 安装类型 | Surface Mount (PLCC socket recommended) | — |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | CMOS, UV-erasable EPROM cell |
| RoHS 状态 | [DATA_NEEDED: rohs status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| 封装 | — | 40-pin CDIP (Ceramic DIP) with quartz window |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |