EP910JC-35 vs EP910DC-35 तुलना
विस्तृत दोनों ओर की तुलना EP910JC-35 द्वारा Altera और EP910DC-35 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910JC-35 | EP910DC-35 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| I/O Pins | 24 | 24 |
| Propagation Delay (max) | 38 ns (tPD) | — |
| अधिकतम क्लॉक फ़्रीक्वेंसी | 28.6 MHz | 37 MHz (typical, internal) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| ऑपरेटिंग तापमान | 0C to 70C (Commercial) | 0 °C to +70 °C (commercial) |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| माउंटिंग प्रकार | Surface Mount (PLCC socket recommended) | — |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | CMOS, UV-erasable EPROM cell |
| RoHS स्थिति | [DATA_NEEDED: rohs status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| पैकेज | — | 40-pin CDIP (Ceramic DIP) with quartz window |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |