EP910LC-35H vs EP910LC-30 Comparison

Detailed side-by-side comparison of EP910LC-35H by Altera and EP910LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LC-35H EP910LC-30
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $25.00 $22.50
Family Classic EPLD (EP910) β€”
Logic Elements 24 macrocells β€”
Equivalent Gates 450 usable gates β€”
Propagation Delay (tpd) 35 ns β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V (nominal, TTL)
Technology CMOS, UV-erasable EPROM β€”
Package 40-pin Ceramic DIP (H suffix) β€”
User I/O Pins 36 β€”
Dedicated Inputs 10 β€”
Operating Temperature [DATA_NEEDED: operating temperature range grade] β€”
Erasure Method UV (quartz window on H package) β€”
Programming Method Altera hardware programmer β€”
Logic Levels TTL compatible β€”
Quiescent Current [DATA_NEEDED: typical ICC value] β€”
Process Node [DATA_NEEDED: process geometry] β€”
Mounting Type Through-hole (Ceramic DIP) β€”
RoHS Status unknown [DATA_NEEDED: RoHS status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) β€”
Device Type β€” EPLD (Erasable Programmable Logic Device)
Macrocell Count β€” 24
Propagation Delay (tPD) β€” 30 ns (max)
Maximum Toggle Frequency β€” 62 MHz
Process Technology β€” CMOS (EPROM-based)
Package Type β€” PDIP-40 (Plastic DIP, through-hole)
Operating Temperature Grade β€” Commercial (0C to +70C)
I/O Pin Count β€” 24
Dedicated Input Pins β€” 36 (including I/O)
Product Terms per Macrocell β€” Up to 16
Programming Technology β€” UV-erasable EPROM cell
Development Tool β€” Altera MAX+PLUS II
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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