EP910LC-35H vs EP910LC-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35H sa pamamagitan ng Altera at EP910LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-35H EP910LC-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) —
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V (nominal, TTL)
Technology CMOS, UV-erasable EPROM —
Packhaging 40-pin Ceramic DIP (H suffix) —
User I/O Pins 36 —
Dedicated Inputs 10 —
Temperature na Operasyon [DATA_NEEDED: operating temperature range grade] —
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer —
Logic Levels TTL compatible —
Kuru-kuryente ng Kapayapaan [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Uri ng Pagpapasok Through-hole (Ceramic DIP) —
Tindminan RoHS unknown [DATA_NEEDED: RoHS status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Device Type — EPLD (Erasable Programmable Logic Device)
Macrocell Count — 24
Propagation Delay (tPD) — 30 ns (max)
Maximum Toggle Frequency — 62 MHz
Process Technology — CMOS (EPROM-based)
Package Type — PDIP-40 (Plastic DIP, through-hole)
Operating Temperature Grade — Commercial (0C to +70C)
I/O Pin Count — 24
Dedicated Input Pins — 36 (including I/O)
Product Terms per Macrocell — Up to 16
Programming Technology — UV-erasable EPROM cell
Development Tool — Altera MAX+PLUS II
Level ng MSL — [DATA_NEEDED: MSL level]

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