EP910LC-35H vs EP910LC-30 比較
詳細並排比較 EP910LC-35H 由 Altera 與 EP910LC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-35H | EP910LC-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910) | — |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (nominal, TTL) |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 40-pin Ceramic DIP (H suffix) | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range grade] | — |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| 靜態電流 | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| 安裝類型 | Through-hole (Ceramic DIP) | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Maximum Toggle Frequency | — | 62 MHz |
| Process Technology | — | CMOS (EPROM-based) |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |