EP910LI-35BF vs EP910LC44 Comparison
Detailed side-by-side comparison of EP910LI-35BF by Altera and EP910LC44 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 β Last Time BuySpecification Comparison
| Parameter | EP910LI-35BF | EP910LC44 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.95 | $8.95 |
| Device Family | Altera Classic EPLD | β |
| Part Number Base | EP910 | β |
| Logic Density | 450 usable gates | β |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | β |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Package | 44-pin PLCC (J-lead) | 44-pin PLCC (J-leaded) |
| Operating Temperature Range | Industrial (LI suffix) | β |
| Technology | CMOS, UV-erasable | β |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| Output Polarity Control | Programmable XOR per macrocell | β |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | β |
| TTL Compatibility | 100% TTL emulation | β |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | β |
| Product Family | β | Classic EPLD (EP910 Series) |
| Manufacturer | β | Altera Corporation (now Intel PSG) |
| Device Type | β | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | β | 240 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Total Input Pins | β | 36 (12 dedicated + 24 I/O as inputs) |
| Global Clock Inputs | β | 2 |
| Propagation Delay (LC grade) | β | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | β | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | β | CMOS |
| Operating Temperature | β | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Architecture | β | AND-OR sum-of-products with programmable macrocell feedback |
| Logic Compatibility | β | TTL-compatible CMOS I/O |
| RoHS Status | β | [DATA_NEEDED: not stated in verified data] |