EP910LI-35BF vs EP910LC44 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LI-35BF disebabkan oleh Altera dan EP910LC44 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP910LC44 EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera

EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera

EP910LC44 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP910LI-35BF EP910LC44
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Device Family Altera Classic EPLD —
Part Number Base EP910 —
Logic Density 450 usable gates —
Macrocells 24 24
Maximum Pin-to-Pin Delay (tpd) 35 ns —
Maximum Toggle Frequency (fmax) 28.6 MHz —
Supply Voltage (VCC) 5 V (nominal) 4.75 V to 5.25 V (5 V nominal)
Kemasan 44-pin PLCC (J-lead) 44-pin PLCC (J-leaded)
Gambaran Suhu Operasi Industrial (LI suffix) —
Technology CMOS, UV-erasable —
Programming Method EPROM/UV-erase programmer (Altera Classic algorithm) EPROM (erasable UV for ceramic; OTP for plastic PLCC)
Output Polarity Control Programmable XOR per macrocell —
Flip-Flop Type Selectable D/T/JK/SR per macrocell —
TTL Compatibility 100% TTL emulation —
Compliance / EOL Status Obsolete - last-time buy exhausted; second-source via Rochester Electronics —
Product Family — Classic EPLD (EP910 Series)
Manufacturer — Altera Corporation (now Intel PSG)
Device Type — Erasable Programmable Logic Device (EPLD)
Total Product Terms — 240
Dedicated Inputs — 12
I/O Pins — 24
Total Input Pins — 36 (12 dedicated + 24 I/O as inputs)
Global Clock Inputs — 2
Propagation Delay (LC grade) — [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data]
Propagation Delay (LC-30 grade) — 33 ns (per EP910LC44-30 verified data)
Process Technology — CMOS
Suhu Operasi — [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data]
Architecture — AND-OR sum-of-products with programmable macrocell feedback
Logic Compatibility — TTL-compatible CMOS I/O
Status RoHS — [DATA_NEEDED: not stated in verified data]

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