EP910LI-35BF vs EP910LC44 对比

详细并排对比 EP910LI-35BF 出自 Altera 和 EP910LC44 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910LI-35BF EP910LC44
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $23.95 $8.95
Device Family Altera Classic EPLD —
Part Number Base EP910 —
Logic Density 450 usable gates —
Macrocells 24 24
Maximum Pin-to-Pin Delay (tpd) 35 ns —
Maximum Toggle Frequency (fmax) 28.6 MHz —
Supply Voltage (VCC) 5 V (nominal) 4.75 V to 5.25 V (5 V nominal)
封装 44-pin PLCC (J-lead) 44-pin PLCC (J-leaded)
工作温度范围 Industrial (LI suffix) —
Technology CMOS, UV-erasable —
Programming Method EPROM/UV-erase programmer (Altera Classic algorithm) EPROM (erasable UV for ceramic; OTP for plastic PLCC)
Output Polarity Control Programmable XOR per macrocell —
Flip-Flop Type Selectable D/T/JK/SR per macrocell —
TTL Compatibility 100% TTL emulation —
Compliance / EOL Status Obsolete - last-time buy exhausted; second-source via Rochester Electronics —
Product Family — Classic EPLD (EP910 Series)
Manufacturer — Altera Corporation (now Intel PSG)
Device Type — Erasable Programmable Logic Device (EPLD)
Total Product Terms — 240
Dedicated Inputs — 12
I/O Pins — 24
Total Input Pins — 36 (12 dedicated + 24 I/O as inputs)
Global Clock Inputs — 2
Propagation Delay (LC grade) — [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data]
Propagation Delay (LC-30 grade) — 33 ns (per EP910LC44-30 verified data)
Process Technology — CMOS
工作温度 — [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data]
Architecture — AND-OR sum-of-products with programmable macrocell feedback
Logic Compatibility — TTL-compatible CMOS I/O
RoHS 状态 — [DATA_NEEDED: not stated in verified data]

数据手册与资源

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