EP910LI-35BF vs EP910LC44 Vergleich
Detaillierter Direktvergleich von EP910LI-35BF von Altera und EP910LC44 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP910LI-35BF | EP910LC44 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $23,95 | $8,95 |
| Device Family | Altera Classic EPLD | — |
| Part Number Base | EP910 | — |
| Logic Density | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Gehäuse | 44-pin PLCC (J-lead) | 44-pin PLCC (J-leaded) |
| Betriebstemperaturbereich | Industrial (LI suffix) | — |
| Technology | CMOS, UV-erasable | — |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| Output Polarity Control | Programmable XOR per macrocell | — |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | — |
| TTL Compatibility | 100% TTL emulation | — |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | — |
| Product Family | — | Classic EPLD (EP910 Series) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Global Clock Inputs | — | 2 |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| Betriebstemperatur | — | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |
| Logic Compatibility | — | TTL-compatible CMOS I/O |
| RoHS-Status | — | [DATA_NEEDED: not stated in verified data] |