EP910PC-15T vs EP910PI-15T Comparison

Detailed side-by-side comparison of EP910PC-15T by Altera and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910PC-15T EP910PI-15T
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $14.20 $10.95
Product Type EPLD (Erasable Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD Altera Classic EPLD (EP910 series)
Macrocell Count 24 β€”
Dedicated Input Pins 10 β€”
Pin-to-Pin Delay (tPD) 15 ns β€”
Speed Grade -15 (15 ns) β€”
Supply Voltage (VCC) 5 V (nominal) β€”
Technology CMOS, UV-erasable / OTP CMOS EEPROM (electrically erasable)
Package 40-pin PDIP (Plastic DIP) 40-pin PDIP (Plastic DIP, R-PDIP-T40)
Mounting Type Through-hole (DIP) Through-Hole
Output Drive Current [DATA_NEEDED: IOL per output] [DATA_NEEDED: per-pin DC output current, mA]
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial temp range]
Logic Capacity 24 macrocells / 72 product terms (typical Classic architecture) β€”
Programming Method JEDEC fuse map via Altera LogicMap / MAX+PLUS II β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
Lead-Free [DATA_NEEDED: lead-free status] β€”
Security Bit Yes (design protection) β€”
Tape and Reel Yes (suffix T) β€”
Macrocells β€” 24
Dedicated Inputs β€” 12
I/O Pins β€” 24
Logic Blocks β€” 6 LABs of 4 macrocells each (Classic architecture)
Supply Voltage β€” 4.5 V to 5.5 V (5 V nominal)
Propagation Delay (tPD) β€” 15 ns max (speed grade -15)
Programming β€” JEDEC-standard, serial/parallel programmer

Datasheets & Resources

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