EP910PC-15T vs EP910PI-15T Vergleich

Detaillierter Direktvergleich von EP910PC-15T von Altera und EP910PI-15T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910PC-15T EP910PI-15T
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $14,20 $10,95
Product Type EPLD (Erasable Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD Altera Classic EPLD (EP910 series)
Macrocell Count 24 —
Dedicated Input Pins 10 —
Pin-to-Pin Delay (tPD) 15 ns —
Speed Grade -15 (15 ns) —
Supply Voltage (VCC) 5 V (nominal) —
Technology CMOS, UV-erasable / OTP CMOS EEPROM (electrically erasable)
Gehäuse 40-pin PDIP (Plastic DIP) 40-pin PDIP (Plastic DIP, R-PDIP-T40)
Montageart Through-hole (DIP) Through-Hole
Output Drive Current [DATA_NEEDED: IOL per output] [DATA_NEEDED: per-pin DC output current, mA]
Betriebstemperatur 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial temp range]
Logic Capacity 24 macrocells / 72 product terms (typical Classic architecture) —
Programming Method JEDEC fuse map via Altera LogicMap / MAX+PLUS II —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
Lead-Free [DATA_NEEDED: lead-free status] —
Security Bit Yes (design protection) —
Tape and Reel Yes (suffix T) —
Macrocells — 24
Dedicated Inputs — 12
I/O Pins — 24
Logic Blocks — 6 LABs of 4 macrocells each (Classic architecture)
Versorgungsspannung — 4.5 V to 5.5 V (5 V nominal)
Propagation Delay (tPD) — 15 ns max (speed grade -15)
Programming — JEDEC-standard, serial/parallel programmer

Datenblätter & Ressourcen

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