EP910PC-15T vs EP910PI-15T 比較
詳細な並列比較: EP910PC-15T メーカー: Altera および EP910PI-15T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PC-15T | EP910PI-15T |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.20 | $10.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Technology | CMOS, UV-erasable / OTP | CMOS EEPROM (electrically erasable) |
| パッケージ | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| 実装タイプ | Through-hole (DIP) | Through-Hole |
| Output Drive Current | [DATA_NEEDED: IOL per output] | [DATA_NEEDED: per-pin DC output current, mA] |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: industrial/commercial temp range] |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| 電源電圧 | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Programming | — | JEDEC-standard, serial/parallel programmer |