EP910PC-15T vs EP910PI-15T Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-15T disebabkan oleh Altera dan EP910PI-15T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910PC-15T EP910PI-15T
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type EPLD (Erasable Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD Altera Classic EPLD (EP910 series)
Macrocell Count 24 —
Dedicated Input Pins 10 —
Pin-to-Pin Delay (tPD) 15 ns —
Speed Grade -15 (15 ns) —
Supply Voltage (VCC) 5 V (nominal) —
Technology CMOS, UV-erasable / OTP CMOS EEPROM (electrically erasable)
Kemasan 40-pin PDIP (Plastic DIP) 40-pin PDIP (Plastic DIP, R-PDIP-T40)
Jenis Pemasangan Through-hole (DIP) Through-Hole
Output Drive Current [DATA_NEEDED: IOL per output] [DATA_NEEDED: per-pin DC output current, mA]
Suhu Operasi 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial temp range]
Logic Capacity 24 macrocells / 72 product terms (typical Classic architecture) —
Programming Method JEDEC fuse map via Altera LogicMap / MAX+PLUS II —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
Lead-Free [DATA_NEEDED: lead-free status] —
Security Bit Yes (design protection) —
Tape and Reel Yes (suffix T) —
Macrocells — 24
Dedicated Inputs — 12
I/O Pins — 24
Logic Blocks — 6 LABs of 4 macrocells each (Classic architecture)
Tegangan Pemberi Arus — 4.5 V to 5.5 V (5 V nominal)
Propagation Delay (tPD) — 15 ns max (speed grade -15)
Programming — JEDEC-standard, serial/parallel programmer

Laporan Datasheet & Sumber

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