EP910PI-12T vs EP910PI-30T Comparison
Detailed side-by-side comparison of EP910PI-12T by Altera and EP910PI-30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-12T | EP910PI-30T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 30 ns |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | 10 |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| Package | 40-pin PDIP (Plastic DIP) | — |
| Process Technology | CMOS | — |
| Operating Temperature | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| RoHS Status | Non-compliant (legacy PDIP package, contains lead) | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | NRND / EOL (mature legacy product) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 480 |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Mounting Type | — | Through-Hole |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |