EP910PI-12T vs EP910PI-30T 比較
詳細な並列比較: EP910PI-12T メーカー: Altera および EP910PI-30T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PI-12T | EP910PI-30T |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $10.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 30 ns |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | 10 |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| パッケージ | 40-pin PDIP (Plastic DIP) | — |
| Process Technology | CMOS | — |
| 動作温度 | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| RoHS ステータス | Non-compliant (legacy PDIP package, contains lead) | [DATA_NEEDED: RoHS status] |
| ライフサイクル状態 | NRND / EOL (mature legacy product) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 480 |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| 実装タイプ | — | Through-Hole |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |