EP910PI-15T vs EP910PC-15T Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-15T sa pamamagitan ng Altera at EP910PC-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PI-15T EP910PC-15T
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Family Altera Classic EPLD (EP910 series) Altera Classic EPLD
Macrocells 24 —
Dedicated Inputs 12 —
I/O Pins 24 —
Logic Blocks 6 LABs of 4 macrocells each (Classic architecture) —
Volte ng Pagbibigay 4.5 V to 5.5 V (5 V nominal) —
Propagation Delay (tPD) 15 ns max (speed grade -15) —
Technology CMOS EEPROM (electrically erasable) CMOS, UV-erasable / OTP
Packhaging 40-pin PDIP (Plastic DIP, R-PDIP-T40) 40-pin PDIP (Plastic DIP)
Uri ng Pagpapasok Through-Hole Through-hole (DIP)
Output Drive Current [DATA_NEEDED: per-pin DC output current, mA] [DATA_NEEDED: IOL per output]
Temperature na Operasyon [DATA_NEEDED: industrial/commercial temp range] 0C to +70C (commercial)
Programming JEDEC-standard, serial/parallel programmer —
Tindminan RoHS [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] [DATA_NEEDED: RoHS compliance status]
Macrocell Count — 24
Dedicated Input Pins — 10
Pin-to-Pin Delay (tPD) — 15 ns
Speed Grade — -15 (15 ns)
Supply Voltage (VCC) — 5 V (nominal)
Logic Capacity — 24 macrocells / 72 product terms (typical Classic architecture)
Programming Method — JEDEC fuse map via Altera LogicMap / MAX+PLUS II
Lead-Free — [DATA_NEEDED: lead-free status]
Security Bit — Yes (design protection)
Tape and Reel — Yes (suffix T)

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