EP910PI-15T vs EP910PC-15T तुलना
विस्तृत दोनों ओर की तुलना EP910PI-15T द्वारा Altera और EP910PC-15T द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910PI-15T | EP910PC-15T |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| सप्लाई वोल्टेज | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | CMOS, UV-erasable / OTP |
| पैकेज | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | 40-pin PDIP (Plastic DIP) |
| माउंटिंग प्रकार | Through-Hole | Through-hole (DIP) |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | [DATA_NEEDED: IOL per output] |
| ऑपरेटिंग तापमान | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| RoHS स्थिति | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | [DATA_NEEDED: RoHS compliance status] |
| Macrocell Count | — | 24 |
| Dedicated Input Pins | — | 10 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Speed Grade | — | -15 (15 ns) |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Logic Capacity | — | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | — | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Security Bit | — | Yes (design protection) |
| Tape and Reel | — | Yes (suffix T) |